AS4C128M32MD2A-25BIN

Alliance Memory
913-4C12832MD2A25BIN
AS4C128M32MD2A-25BIN

Mfr.:

Description:
DRAM LPDDR2, 4G, 128M X 32, 1.2V, 134 BALL BGA, 400MHZ, Industrial TEMP - Tray

Datasheet:
ECAD Model:
Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.
More Information
Learn more about Alliance Memory AS4C128M32MD2A-25BIN

Product Attribute Attribute Value Select Attribute
Alliance Memory
Product Category: DRAM
RoHS:  
SDRAM Mobile - LPDDR2
4 Gbit
32 bit
400 MHz
FBGA-134
128 M x 32
5.5 ns
1.14 V
1.95 V
- 40 C
+ 85 C
AS4C128M32MD2A-25
Tray
Brand: Alliance Memory
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 168
Subcategory: Memory & Data Storage
Supply Current - Max: 130 mA
Unit Weight: 2,191 g
Products found:
To show similar products, select at least one checkbox
Select at least one checkbox above to show similar products in this category.
Attributes selected: 0

Datasheet

Compliance Codes
CNHTS:
8542329010
CAHTS:
8542320020
USHTS:
8542320036
MXHTS:
8542320201
ECCN:
EAR99
Origin Classifications
Country of Origin:
Taiwan
Assembly Country of Origin:
Taiwan
Country of Diffusion:
Taiwan
The country is subject to change at the time of shipment.

DDR2 SDRAM

Alliance Memory DDR2 SDRAM is designed to comply with DDR2 SDRAM key features. Features such as posted CAS# with additive latency, Write latency=Read latency -1, and On-Die Termination (ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style.

Low-Power DDR2 SDRAM

Alliance Memory Low-Power DDR2 SDRAM are high-speed CMOS and dynamic-access memory internally configured as an 8-bank device. These DDR2 SDRAM feature 4-bit pre-fetch DDR architecture, programmable READ and WRITE latencies, auto Temperature Compensated Self Refresh (TCSR), and clock stop capability. The DDR2 SDRAM reduces the number of input pins in the system by using a double data rate architecture on the Command/Address (CA) bus. This CA bus transmits address, command, and bank information. These DDR2 SDRAM can achieve high-speed operation by using a double data rate architecture on the DQ (bidirectional/differential data bus) pins.

Availability

Stock:
0

You can still purchase this product for backorder.

On Order:
124
Expected 21/10/2026
Factory Lead Time:
20
Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:

Pricing (EUR)

Qty. Unit Price
Ext. Price
47,15 € 47,15 €
43,53 € 435,30 €
42,11 € 1 052,75 €
41,06 € 2 053,00 €
39,56 € 3 956,00 €

An unexpected error has occurred.


Have a question? Please visit the Help Centre.
For questions about a specific order, please log in to your account.

If you encounter further problems, please contact us on 800-346-6873 or email help@mouser.com.