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25CS320-E/SN

Name: Microchip 25CS320-E/SN
Brand: Microchip Technology
SKU: 579-25CS320-E/SN
Price: 0.46 EUR
Availability: InStock

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Mouser No:

579-25CS320-E/SN

Mfr. No:

25CS320-E/SN

Mfr.:

Microchip Technology

Description:

EEPROM 32 Kbit SPI SERIAL EEPROM w/ECC, 8-SOIC Bulk, 125C Ext Temp

Lifecycle:

New Product:

New from this manufacturer.

Datasheet:

25CS320-E/SN Datasheet (PDF)

ECAD Model:

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More Information

Learn more about Microchip Technology 25CS320-E/SN

In Stock: 525

Stock:: 525 Can Dispatch Immediately

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Factory Lead Time:: 4 Weeks Estimated factory production time for quantities greater than shown.

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Pricing (EUR)

Qty.	Unit Price	Ext. Price
	0,464 €	0,46 €
	0,458 €	4,58 €
	0,439 €	10,98 €
	0,421 €	42,10 €

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Microchip
Product Category:	EEPROM
RoHS:
Memory Size:	32 kbit
Interface Type:	SPI
Maximum Clock Frequency:	20 MHz
Organisation:	4 k x 8
Package/Case:	SOIC-8
Access Time:	20 ns
Supply Voltage - Min:	1.7 V
Supply Voltage - Max:	5.5 V
Mounting Style:	SMD/SMT
Data Retention:	200 Year
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 125 C
Packaging:	Tube
Active Read Current - Max:	5 mA
Brand:	Microchip Technology
Operating Supply Current:	10 uA
Product Type:	EEPROM
Factory Pack Quantity:	100
Subcategory:	Memory & Data Storage

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Filter Document:

Datasheet

25CS320-E/SN Datasheet (PDF)

PCN

Product Change Notification 2025-5-28 (PDF)

TARIC:: 8542327500
USHTS:: 8542320051
ECCN:: EAR99

25CS320 32-Kbit SPI Serial EEPROM

Microchip Technology 25CS320 32-Kbit SPI Serial EEPROM uses an SPI-compatible bus organized into 4096 bytes of 8-bits each (4KB). Microchip Technology 25CS320 is designed for consumer, industrial, and automotive applications and offers reliable, nonvolatile memory storage with a wide operating voltage range of 1.7V to 5.5V. The device requires a clock input (SCK), data input (SI), and data output (SO) lines, with access controlled via a Chip Select (CS) input. It also features a pause function, allowing the host to handle higher-priority tasks while ignoring input transitions, except for Chip Select.