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LS2048ASN7QQB

Name: NXP LS2048ASN7QQB
Brand: NXP Semiconductors
SKU: 771-LS2048ASN7QQB
Price: 345.1 EUR
Availability: InStock

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See Product Specifications

Mouser No:

771-LS2048ASN7QQB

Mfr. No:

LS2048ASN7QQB

Mfr.:

NXP Semiconductors

Description:

Microprocessors - MPU Layerscape 64-bit Arm Cortex-A72, Quad-core, 1.6GHz, 0 to 105C, Security disabled, AIOP

ECAD Model:

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Shipping Alert:

This product may require additional documentation to export from the United States.

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	NXP
Product Category:	Microprocessors - MPU
Delivery Restrictions:	This product may require additional documentation to export from the United States.
RoHS:
Core:	ARM Cortex A72
Number of Cores:	4 Core
Data Bus Width:	64 bit
Maximum Clock Frequency:	1.6 GHz
Package/Case:	FCPBGA-1292
L1 Cache Instruction Memory:	48 kB
L1 Cache Data Memory:	32 kB
Operating Supply Voltage:	900 mV to 1.05 V
Series:	LS2048A
Mounting Style:	SMD/SMT
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 105 C
Packaging:	Tray
Brand:	NXP Semiconductors
Data RAM Size:	128 kB
I/O Voltage:	1.2 V, 1.8 V
Interface Type:	Ethernet, I2C, PCI-e, Serial, USB
L2 Cache Instruction / Data Memory:	2 x 1 MB
Memory Type:	DDR4 SDRAM
Moisture Sensitive:	Yes
Number of Timers/Counters:	4 Timer
Processor Series:	QorIQ Layerscape LS2048A
Product Type:	Microprocessors - MPU
Factory Pack Quantity:	21
Subcategory:	Microprocessors - MPU
Tradename:	QorIQ
Watchdog Timers:	Watchdog Timer
Part # Aliases:	935371387557

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Compliance Codes

TARIC:: 8542319000
CNHTS:: 8542319091
USHTS:: 8542310045
ECCN:: 3A991.a.1

Origin Classifications

Country of Origin:: Korea, Republic of
Assembly Country of Origin:: Korea, Republic of
Country of Diffusion:: Taiwan

The country is subject to change at the time of shipment.

Layerscape Architecture

NXP Layerscape Architecture is the underlying system architecture of the QorIQ® LS series processors. The architecture enables next-generation networks with up to 100Gb/s performance and enhanced packet processing capabilities. Design effort is simplified with a standard, open programming model and a software-aware architecture framework. This design enables customers to fully exploit the underlying hardware for maximum optimization, with the capability to easily adapt to network changes for real-time soft control over the network. A uniform hardware and software model provides the compatibility and scalability required for designing end-to-end networking equipment from home-to carrier-class products. The core-agnostic architecture incorporates the optimum core for the given application: Arm® cores or Power Architecture® cores.