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STMicroelectronics SPC570S MCUs

STMicroelectronics SPC570S MCUs are 32-bit automotive microcontrollers designed for next-generation, entry-level vehicle safety like ABS and airbags. This system-on-chip (SoC) device is ASIL-D compliant and operates at speeds up to 80MHz. For application development, the MCUs are compatible with the current Power Architecture® development infrastructure and are supported with software drivers, operating systems, and configuration codes. These MCUs offer high-performance processing with low power consumption.

Features

  • High performance e200z0h dual core
    • 32-bit Power Architecture technology CPU
    • Core frequency as high as 80MHz
    • Single issue 4-stage pipeline in-order execution core
    • Variable Length Encoding (VLE)
  • Up to 544KB (512KB code + 32KB data, suitable for EEPROM emulation) on-chip flash memory: supports read during program and erase
  • operations, and multiple blocks allowing EEPROM emulation
  • Up to 48KB on-chip general-purpose SRAM
  • Multi-channel direct memory access controller (eDMA paired in lockstep) with 16 channels
  • Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
  • Nexus Class 3 debug and trace interface
  • Communication interfaces:
    • 2 LINFlexD modules
    • 3 deserial serial peripheral interface (DSPI) modules
    • Up to 2 FlexCAN interfaces with 32 message buffers each
  • On-chip CAN/UART Bootstrap loader with Boot Assisted Flash (BAF). Physical Interface (PHY) can be:
    • UART
    • CAN
  • 2 enhanced 12-bit SAR analog converters:
    • 1.5μs conversion time (12MHz)
    • 16 physical channels (fully shared between the 2 SARADC units)
    • Supervisor ADC concept
    • Programmable Cross Triggering Unit (CTU)
  • 4 general purpose eTimer units (6 channels each)
  • Single 3.3V or 5V voltage supply
  • Junction temperature range -40°C to 150°C
  • Comprehensive new generation ASILD safety concept:
    • Safety of bus masters (core+INTC, DMA) by delayed lockstep approach
    • Safety of storage (Flash, SRAM) by mainly ECC
    • Safety of the data path to storage and periphery by mainly End-to-End EDC (E2E EDC)
    • Clock and power, generation and distribution, supervised by dedicated monitors
    • Fault Collection and Control Unit (FCCU) for collection and reaction to failure notifications
    • Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
    • Boot time MBIST and LBIST for latent
    • faults
    • Check of safety mechanisms availability and error reaction path functionality by dedicated mechanisms
    • Safety of the periphery by application-level measures supported by replicated peripheral bridges and by LBIST
    • Further measures on dedicated peripherals (e.g. ADC supervisor)
    • Junction temperature sensor
    • 8-region system memory protection unit (SMPU) with process ID support (tasks isolation)
    • Enhanced SW watchdog
    • Cyclic redundancy check (CRC) unit

SPC570S MCUs Block Diagram

Block Diagram - STMicroelectronics SPC570S MCUs

Associated Tool

STMicroelectronics SPC570S-DISP Discovery Evaluation Board

Offers full access to CPUs, I/O signals and peripherals to discover SPC57 S Microcontrollers.

Learn Moreabout STMicroelectronics SPC570S-DISP Discovery Evaluation Board View Productsrelated to STMicroelectronics SPC570S-DISP Discovery Evaluation Board

Associated Products

STMicroelectronics SPC5 32-bit Automotive Microcontrollers

Designed using Power Architecture® and ST's embedded Flash technology.

Learn Moreabout STMicroelectronics SPC5 32-bit Automotive Microcontrollers View Productsrelated to STMicroelectronics SPC5 32-bit Automotive Microcontrollers
Published: 2016-03-16 | Updated: 2022-03-11