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Texas Instruments CDCE6214/CDCE6214-Q1 Clock Generator

Texas Instruments CDCE6214/CDCE6214-Q1 Ultra-Low Power Clock Generators generate five independent clock outputs that are selectable between various modes of drivers. Other applications include data center and enterprise computing for PCs, notebooks, and multi-function printers. The four-channel, medium-grade jitter clock generators have an input source that could be a single-ended or differential input clock source or a crystal. CDCE6214/CDCE6214-Q1 clock generators feature a frac-N PLL to synthesize unrelated base frequencies from any input frequency. The devices can be configured through the I2C interface. GPIO pins can be used in Pin Mode without the serial interface to configure the clock generators into distinctive configurations. The Texas Instruments CDCE6214-Q1 devices are AEC-Q100 qualified for automotive applications.

Features

  • AEC-Q100 qualified for automotive applications
    • -40°C to +105°C temperature grade
  • Configurable high-performance, low-power, frac-N PLL with RMS jitter with spurs (12kHz – 20MHz, FOUT > 100MHz) as:
    • Integer mode
      • 350fs typical, 600fs (max.) differential output
      • 1.0ps typical, 1.5 ps (max.) LVCMOS output
    • Fractional mode
      • 1.7ps typical, 2.1ps (max.) differential output
      • 2.0ps typical, 4.0 ps (max.) LVCMOS output
  • Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
  • 2.335GHz to 2.625GHz internal VCO
  • 65mA for a 4-output (typ.) channel, 23mA for 1-output channel power consumption
  • Universal clock input, two reference inputs for redundancy
    • 10MHz to 200MHz differential AC-coupled or LVCMOS
    • 10MHz to 50MHz crystal
  • Flexible output clock distribution
    • Four-channel dividers: Up to 5 unique output frequencies from 24kHz to 328.125MHz
    • Combination of LVDS-like, LP-HCSL, or LVCMOS outputs on OUT0–OUT4 pins
    • Glitchless output divider switching and output channel synchronization
    • Individual output is enabled through GPIO and register
  • Frequency margining options
    • DCO mode: frequency increment/decrement with 10ppb or less step size
  • 100kHz to 1.6MHz fully integrated, configurable loop bandwidth
  • 1.8V/2.5V/3.3V single- or mixed-supply for level translation
  • Configurable GPIOs and flexible configuration options
    • Up to 400kHz I2C-compatible interface
      • Integrated EEPROM with two pages and an external select pin
  • Supports 100Ω systems
  • Low electromagnetic emissions
  • A small footprint of 24-pin VQFN (4mm×4mm)

Datasheets

Block Diagram

Block Diagram - Texas Instruments CDCE6214/CDCE6214-Q1 Clock Generator

Associated Development Tool

Published: 2019-12-27 | Updated: 2024-02-22