XMOS XCORE.AI Multicore Microcontrollers

XMOS XCORE.AI Multicore Microcontrollers offer a comprehensive range of 32-bit multicore MCUs that feature the low latency and timing determinism of the xCORE architecture to mainstream embedded applications. The xCORE multicore microcontrollers perform multiple real-time tasks simultaneously and communicate between tasks via a high-speed network, unlike conventional microcontrollers.

The XMOS XCORE.AI Multicore Microcontrollers allow users to implement functions that traditionally demand dedicated hardware.

Features

Multicore microcontroller with advanced multicore RISC architecture
- 16 real-time logical cores on 2 xCORE tiles
- Cores share up to 1600MIPS
  - Up to 3200MIPS in dual-issue mode
  - Up to 1600MFLOPS
- Each logical core has:
  - Guaranteed throughput of between 1/5 and 1/8 of tile MIPS
  - 16 x 32-bit dedicated registers
- 229 high-density 16/32-bit instructions
  - All have single-clock-cycle execution (except for divide)
  - 32 x 32-> 64-bit MAC instructions for DSP, arithmetic, and cryptographic functions
- Vector unit, capable of:
  - Up to eight words, 16 half-words, or 32-byte multiply-adds
  - Quad complex multiply, or 256-bit-wide multiply-adds
USBPHY is fully compliant with the USB 2.0 specification
MIPI receiver, up to two lanes, up to 1.5Gbit/s
Application PLL with fractional control
Programmable I/O
- 128 general-purpose I/O pins, configurable as input or output
  - Up to 32 x 1-bit port, 12 x 4-bit port, 8 x 8-bit port, 4 x 16-bit port, 2 x 32-bit port
  - 8 xCONNECT links
- Port sampling rates of up to 60MHz with respect to an external clock
- 64 channel ends (32 per tile) for communication with other cores, on or off-chip
- 1.8V/3.3V IO with programmable drive strength

Memory
- 1024KB internal single-cycle SRAM (512KB per tile) for code and data storage
- LPDDR-1 interface for optional external memory
- 8KB internal OTP (shared between tiles or split, providing 4KB per tile) for application boot code
Hardware resources
- 12 clock blocks (six per tile)
- 20 timers (10 per tile)
- Eight locks (four per tile)
JTAG module for on-chip debug
Security features
- Programming the lock disables debug and prevents read-back of memory contents
- AES bootloader ensures the secrecy of IP held on external flash memory
Ambient temperature range
- Commercial qualification at 0°C to +70°C
- Industrial qualification at -40°C to +85°C
Speed grade
- 24: 600MHz; up to 2400MIPS, 1200MFLOP/s, 38.4GMACC/s
- 32: 800MHz; up to 3200MIPS, 1600MFLOP/s, 51.2GMACC/s
Power consumption
- Active: 203mW at 600MHz (typical)
- Active: 270mW at 800MHz (typical)
- Standby: 5mA (typical)
265-pin FBGA package 0.8mm pitch