Texas Instruments RM44Lx20 RISC Flash Arm Cortex-R4F Microcontroller
Texas Instruments RM44Lx20 RISC Flash Arm Cortex-R4F Microcontroller (MCU) is part of the Hercules RM series of high-performance industrial-grade ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to assist in the development of IEC 61508 functional safety applications. The RM44Lx20 device has on-chip diagnostic features. These include dual CPUs in lockstep; CPU and memory Built-In Self-Test (BIST) logic; ECC on both the flash and the SRAM; parity on peripheral memories; and loopback capability on most peripheral I/Os.
The RM44Lx20 device integrates the ARM Cortex-R4F floating-point CPU, which offers an efficient 1.66 DMIPS/MHz and has configurations that can run up to 180MHz, providing up to 298 DMIPS. The RM44Lx20 device supports the little-endian [LE] format.
The RM44Lx20 device has up to 1MB of integrated flash and 128KB of RAM configurations with single-bit error correction and double-bit error detection. The flash memory on this device is nonvolatile, electrically erasable and programmable, and is implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3V supply input (same level as the I/O supply) for all read, program, and erase operations. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and doubleword modes throughout the supported frequency range.
The Texas Instruments RM44Lx20 device features peripherals for real-time control-based applications, including two Next-Generation High-End Timer (N2HET) timing coprocessors with up to 44 total I/O terminals, seven Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.
Features
- High-performance microcontroller (MCU) for Safety-Critical applications
- Dual CPUs running in lockstep
- ECC on Flash and RAM interfaces
- Built-In Self-Test (BIST) for CPU and on-chip RAMs
- Error signaling module with error pin
- Voltage and clock monitoring
- ARM Cortex-R4F 32-Bit RISC CPU
- 1.66 DMIPS/MHz with 8-stage pipeline
- FPU with single and double precision
- 12-region Memory Protection Unit (MPU)
- Open architecture with third-party support
- Operating conditions
- Up to 180MHz system clock
- 1.14V to 1.32V core supply voltage (VCC)
- 3.0V to 3.6V I/O supply voltage (VCCIO)
- Integrated memory
- Up to 1MB of Flash with ECC
- 128KB of RAM with ECC
- 64KB of Flash for emulated EEPROM with ECC
- Common platform architecture
- Consistent memory map across the family
- Real-Time Interrupt timer (RTI) OS timer
- 128-channel Vectored Interrupt Module (VIM)
- 2-channel Cyclic Redundancy Checker (CRC)
- Direct Memory Access (DMA) controller
- 16 channels and 32 peripheral requests
- Parity for control packet RAM
- DMA accesses protected by dedicated MPU
- Frequency-Modulated Phase-Locked Loop (FMPLL) with built-in slip detector
- IEEE 1149.1 JTAG, Boundary Scan, and ARM CoreSight components
- Advanced JTAG Security Module (AJSM)
- Up to 64 General-Purpose I/O (GIO) pins
- Up to 16 GIO pins with interrupt generation capability
- Enhanced timing peripherals
- 7 Enhanced Pulse Width Modulator (ePWM) modules
- 6 Enhanced Capture (eCAP) modules
- 2 Enhanced Quadrature Encoder Pulse (eQEP) modules
- Two Next Generation High-End Timer (N2HET) modules
- N2HET1 - 32 programmable channels
- N2HET2 - 18 programmable channels
- 160-word instruction RAM with parity protection each
- Each N2HET includes a hardware angle generator
- Dedicated High-End Timer Transfer Unit (HTU) for each N2HET
- Two 12-bit multibuffered ADC modules
- ADC1 - 24 channels
- ADC2 - 16 channels
- 16 shared channels
- 64 result buffers with parity protection each
- Multiple communication interfaces
- Up to three CAN Controllers (DCANs)
- 64 mailboxes with parity protection each
- Compliant to CAN protocol version 2.0A and 2.0B
- Inter-Integrated Circuit (I2C)
- 3 Multibuffered Serial Peripheral Interfaces (MibSPIs)
- 128 words with parity protection each
- Eight transfer groups
- One standard Serial Peripheral Interface (SPI) module
- Two UART (SCI) interfaces, one with Local Interconnect Network (LIN 2.1) interface support
- Up to three CAN Controllers (DCANs)
- Packages
- 144-pin quad flatpack (PGE) [Green]
- 100-pin quad flatpack (PZ) [Green]
Applications
- Industrial safety applications
- Industrial automation
- Safe Programmable Logic Controllers (PLCs)
- Power generation and distribution
- Turbines and windmills
- Elevators and escalators
- Medical applications
- Ventilators
- Defibrillators
- Infusion and insulin pumps
- Radiation therapy
- Robotic surgery
Functional Block Diagram
Related Development Tools
Texas Instruments TMDSEMU560V2STM-UE XDS560v2 System Trace
Debug probes that support both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).